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1 LTC1860/ltc1861 18601f applicatio s u features descriptio u typical applicatio u m power, 12-bit, 250ksps 1- and 2-channel adcs in msop single 5v supply, 250ksps, 12-bit sampling adc supply current vs sampling frequency the ltc ? 1860/ltc1861 are 12-bit a/d converters that are offered in msop and so-8 packages and operate on a single 5v supply. at 250ksps, the supply current is only 850 m a. the supply current drops at lower speeds because the LTC1860/ltc1861 automatically power down to a typical supply current of 1na between conversions. these 12-bit switched capacitor successive approximation adcs include sample-and-holds. the LTC1860 has a differential analog input with an adjustable reference pin. the ltc1861 offers a software-selectable 2-channel mux and an ad- justable reference pin on the msop version. the 3-wire, serial i/o, msop or so-8 package and extremely high sample rate-to-power ratio make these adcs ideal choices for compact, low power, high speed systems. these adcs can be used in ratiometric applications or with external references. the high impedance analog inputs and the ability to operate with reduced spans down to 1v full scale, allow direct connection to signal sources in many applications, eliminating the need for external gain stages. n 12-bit 250ksps adcs in msop package n single 5v supply n low supply current: 850 m a (typ) n auto shutdown reduces supply current to 2 m a at 1ksps n true differential inputs n 1-channel (LTC1860) or 2-channel (ltc1861) versions n spi/microwire tm compatible serial i/o n high speed upgrade to ltc1286/ltc1298 n pin compatible with 16-bit ltc1864/ltc1865 , ltc and lt are registered trademarks of linear technology corporation. n high speed data acquisition n portable or compact instrumentation n low power battery-operated instrumentation n isolated and/or remote data acquisition microwire is a trademark of national semiconductor corporation. 1 2 3 4 8 7 6 5 v ref in + in gnd v cc sck sdo conv LTC1860 1860 ta01 analog input 0v to 5v 5v 1 m f serial data link to asic, pld, mpu, dsp or shift registers sampling frequency (khz) 0.01 supply current ( a) 1000 100 10 1 0.1 0.01 100 1860 ta02 0.1 1 10 1000 ( datasheet : )
2 LTC1860/ltc1861 18601f power dissipation .............................................. 400mw operating temperature range LTC1860c/ltc1861c ............................. 0 c to 70 c LTC1860i/ltc1861i .......................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c supply voltage (v cc ) ................................................. 7v ground voltage difference agnd, dgnd ltc1861 msop package ........... 0.3v analog input .................... (gnd C 0.3v) to (v cc + 0.3v) digital input ..................................... (gnd C 0.3v) to 7v digital output .................. (gnd C 0.3v) to (v cc + 0.3v) (notes 1, 2) order part number ms8 part marking order part number LTC1860cms8 LTC1860ims8 ltwr ltws ms part marking t jmax = 150 c, q ja = 210 c/w t jmax = 150 c, q ja = 175 c/w 1 2 3 4 v ref in + in? gnd 8 7 6 5 v cc sck sdo conv top view ms8 package 8-lead plastic msop absolute axi u rati gs w ww u package/order i for atio uu w ltc1861cms ltc1861ims ltwt ltwu consult ltc marketing for parts specified with wider operating temperature ranges. parameter conditions min typ max units resolution l 12 bits no missing codes resolution l 12 bits inl (note 3) l 1lsb transition noise 0.07 lsb rms gain error l 20 mv offset error LTC1860 so-8 and msop, ltc1861 msop l 2 5mv ltc1861 so-8 l 3 7mv input differential voltage range v in = in + C in C l 0v ref v absolute input range in + input C 0.05 v cc + 0.05 v in C input C 0.05 v cc /2 v v ref input range LTC1860 s0-8 and msop, ltc1861 msop 1 v cc v analog input leakage current (note 4) l 1 m a c in input capacitance in sample mode 12 pf during conversion 5 pf the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v, v ref = 5v, f sck = f sck(max) as defined in recommended operating conditions, unless otherwise noted. co verter a d ultiplexer characteristics u w u order part number s8 part marking LTC1860cs8 LTC1860is8 1860 1860i 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so v ref in + in gnd v cc sck sdo conv order part number s8 part marking ltc1861cs8 ltc1861is8 1861 1861i t jmax = 150 c, q ja = 210 c/w t jmax = 150 c, q ja = 175 c/w 1 2 3 4 5 conv ch0 ch1 agnd dgnd 10 9 8 7 6 v ref v cc sck sdo sdi top view ms package 10-lead plastic msop 1 2 3 4 8 7 6 5 top view s8 package 8-lead plastic so conv ch0 ch1 gnd v cc sck sdo sdi
3 LTC1860/ltc1861 18601f the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v, v ref = 5v, unless otherwise noted. t a = 25 c. v cc = 5v, f sample = 250khz, unless otherwise specified. symbol parameter conditions min typ max units snr signal-to-noise ratio 72 db s/(n + d) signal-to-noise plus distortion ratio 100khz input signal 71 db thd total hamonic distortion up to 5th harmonic 100khz input signal 77 db full power bandwidth 20 mhz full linear bandwidth s/(n + d) 3 68db 125 khz dy a ic accuracy u w digital a d dc electrical characteristics u the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. reco e ded operati g co ditio s u u u uw w symbol parameter conditions min typ max units v ih high level input voltage v cc = 5.25v l 2.4 v v il low level input voltage v cc = 4.75v l 0.8 v i ih high level input current v in = v cc l 2.5 m a i il low level input current v in = 0v l C 2.5 m a v oh high level output voltage v cc = 4.75v, i o = 10 m a l 4.5 4.74 v v cc = 4.75v, i o = 360 m a l 2.4 4.72 v v ol low level output voltage v cc = 4.75v, i o = 1.6ma l 0.4 v i oz hi-z output leakage conv = v cc l 3 m a i source output source current v out = 0v C 25 ma i sink output sink current v out = v cc 20 ma i ref reference current (LTC1860 so-8, msop and conv = v cc l 0.001 3 m a ltc1861 msop) f smpl = f smpl(max) l 0.05 0.1 ma i cc supply current conv = v cc after conversion l 0.001 3 m a f smpl = f smpl(max) l 0.85 1.3 ma p d power dissipation f smpl = f smpl(max) 4.25 mw symbol parameter conditions min typ max units v cc supply voltage 4.75 5.25 v f sck clock frequency l dc 20 mhz t cyc total cycle time 12 ? sck + t conv m s t smpl analog input sampling time LTC1860 12 sck ltc1861 10 sck t suconv setup time conv before first sck -, 30 ns (see figure 1) t hdi holdtime sdi after sck - ltc1861 15 ns t sudi setup time sdi stable before sck - ltc1861 15 ns t whclk sck high time f sck = f sck(max) 40% 1/f sck t wlclk sck low time f sck = f sck(max) 40% 1/f sck t whconv conv high time between data t conv m s transfer cycles t wlconv conv low time during data transfer 12 sck t hconv hold time conv low after last sck - 13 ns
4 LTC1860/ltc1861 18601f note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all voltage values are with respect to gnd. note 3: integral nonlinearity is defined as deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 4: channel leakage current is measured while the part is in sample mode. symbol parameter conditions min typ max units t conv conversion time (see figure 1) l 2.75 3.2 m s f smpl(max) maximum sampling frequency l 250 khz t ddo delay time, sck to sdo data valid c load = 20pf 15 20 ns l 25 ns t dis delay time, conv - to sdo hi-z l 30 60 ns t en delay time, conv to sdo enabled c load = 20pf l 30 60 ns t hdo time output data remains c load = 20pf l 510 ns valid after sck t r sdo rise time c load = 20pf 8 ns t f sdo fall time c load = 20pf 4 ns the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc = 5v, v ref = 5v, f sck = f sck(max) as defined in recommended operating conditions, unless otherwise noted. ti i g characteristics u w typical perfor a ce characteristics uw supply current vs sampling frequency supply current vs temperature sleep current vs temperature sampling frequency (khz) 0.01 supply current ( a) 1000 100 10 1 0.1 0.01 100 1860/61 g01 0.1 1.0 10 1000 conv low = 800ns t a = 25 c v cc = 5v temperature ( c) ?0 supply current ( a) 1000 800 600 400 200 0 0 50 75 1860/61 g02 ?5 25 100 125 conv high = 3.2 s f smpl = 250khz v cc = 5v v ref = 5v temperature ( c) ?0 sleep current (na) 1000 900 800 700 600 500 400 300 200 100 0 0 50 75 1860/61 g03 ?5 25 100 125 conv = v cc = 5v
5 LTC1860/ltc1861 18601f reference current vs sample rate reference current vs temperature reference current vs reference voltage typical inl curve typical dnl curve analog input leakage vs temperature sample rate (khz) 0 reference current ( a) 60 50 40 30 20 10 0 50 100 150 200 1860/61 g04 250 conv is low for 800ns t a = 25 c v cc = 5v v ref = 5v temperature ( c) ?0 reference current ( a) 55 54 53 52 51 50 49 48 47 46 45 0 50 75 1860/61 g05 ?5 25 100 125 f s = 250khz v cc = 5v v ref = 5v v ref (v) 0 i ref ( a) 60 50 40 30 20 10 0 1234 1860/61 g06 5 f s = 250khz t a = 25 c v cc = 5v code 0 inl coc error (lsbs) 4096 1860/61 g07 1024 2048 3072 1.0 0.5 0 0.5 ?.0 512 1536 2560 3584 t a = 25 c v cc = 5v v ref = 5v code 0 dnl eoc error (lsbs) 4096 1860/61 g07 1024 2048 3072 1.0 0.5 0 0.5 ?.0 512 1536 2560 3584 t a = 25 c v cc = 5v v ref = 5v temperature ( c) ?0 analog input leakage (na) 100 1860/61 g09 050 100 75 50 25 0 25 25 75 125 v cc = 5v v ref = 5v conv = 0v typical perfor a ce characteristics uw change in offset error vs reference voltage change in offset vs temperature change in gain error vs reference voltage reference voltage (v) 0 change in offset error (lsb) 5 4 3 2 1 0 ? ? ? ? ? 4 1860/61 g10 1 2 3 5 t a = 25 c v cc = 5v temperature ( c) ?0 change in offset (lsb) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 ?.0 0 50 75 1860/61 g11 ?5 25 100 125 v cc = 5v reference voltage(v) 0 change in gain error (lsb) 5 4 3 2 1 0 ? ? ? ? ? 2 4 5 1860/61 g12 1 3 v cc = 5v t a = 25 c
6 LTC1860/ltc1861 18601f typical perfor a ce characteristics uw change in gain error vs temperature temperature ( c) ?0 change in gain error (lsb) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 ?.0 0 50 75 1860/61 g13 ?5 25 100 125 v cc = 5v v ref = 5v v ref (pin 1): reference input. the reference input defines the span of the a/d converter and must be kept free of noise with respect to gnd. in + , in C (pins 2, 3): analog inputs. these inputs must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. conv (pin 5): convert input. a logic high on this input starts the a/d conversion process. if the conv input is left uu u pi fu ctio s LTC1860 high after the a/d conversion is finished, the part powers down. a logic low on this input enables the sdo pin, allowing the data to be shifted out. sdo (pin 6): digital data output. the a/d conversion result is shifted out of this pin. sck (pin 7): shift clock input. this clock synchronizes the serial data transfer. v cc (pin 8): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. input level (db) ?0 signal-to-(noise + distortion) (db) 1195 g20 ?0 ?5 ?5 ?5 ?0 5 ?0 0 80 70 60 50 40 30 20 10 0 f in = 10khz t a = 25 c v cc = 5v f (khz) 0607090 amplitude (db) 0 ?0 ?0 ?0 ?0 ?00 ?20 10 20 30 80 40 1860/61 g15 100 50 f s = 204.1khz f in = 99.5khz t a = 25 c v cc = 5v f in (khz) signal-to-(noise + distortion) (db) 100 90 80 70 60 50 40 30 20 10 0 1 100 1000 10000 1860/61 g16 10 t a = 25 c v cc = 5v v in = 0db snr sinad f in (khz) 1 total harmonic distortion (db) 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 10 100 1000 1860/61 g17 t a = 25 c v cc = 5v v in = 0db f in (khz) 1 spurious free dynamic range (db) 100 90 80 70 60 50 40 30 20 10 0 10 100 1000 1860/61 g18 t a = 25 c v cc = 5v v in = 0db 4096 point fft signal-to-(noise + distortion) vs input level signal-to-(noise + distortion) vs f in total harmonic distortion vs f in spurious free dynamic range vs f in
7 LTC1860/ltc1861 18601f conv (pin 1): convert input. a logic high on this input starts the a/d conversion process. if the conv input is left high after the a/d conversion is finished, the part powers down. a logic low on this input enables the sdo pin, allowing the data to be shifted out. ch0, ch1 (pins 2, 3): analog inputs. these inputs must be free of noise with respect to gnd. gnd (pin 4): analog ground. gnd should be tied directly to an analog ground plane. sdi (pin 5): digital data input. the a/d configuration word is shifted into this input. sdo (pin 6): digital data output. the a/d conversion result is shifted out of this output. sck (pin 7): shift clock input. this clock synchronizes the serial data transfer. v cc (pin 8): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. v ref is tied internally to this pin. ltc1861 (so-8 package) ltc1861 (msop package) conv (pin 1): convert input. a logic high on this input starts the a/d conversion process. if the conv input is left high after the a/d conversion is finished, the part powers down. a logic low on this input enables the sdo pin, allowing the data to be shifted out. ch0, ch1 (pins 2, 3): analog inputs. these inputs must be free of noise with respect to agnd. agnd (pin 4): analog ground. agnd should be tied directly to an analog ground plane. dgnd (pin 5): digital ground. dgnd should be tied directly to an analog ground plane. sdi (pin 6): digital data input. the a/d configuration word is shifted into this input. sdo (pin 7): digital data output. the a/d conversion result is shifted out of this output. sck (pin 8): shift clock input. this clock synchronizes the serial data transfer. v cc (pin 9): positive supply. this supply must be kept free of noise and ripple by bypassing directly to the analog ground plane. v ref (pin 10): reference input. the reference input de- fines the span of the a/d converter and must be kept free of noise with respect to agnd. uu u pi fu ctio s fu n ctio n al block diagra uu w 1860/61 bd 12-bit sampling adc bias and shutdown convert clk serial port 12-bits in + (ch0) in (ch1) v cc v ref sdo gnd conv (sdi) sck pin names in parentheses refer to ltc1861 data out data in +
8 LTC1860/ltc1861 18601f load circuit for t ddo , t r , t f , t dis and t en voltage waveforms for sdo rise and fall times, t r , t f voltage waveforms for sdo delay times, t ddo and t hdo voltage waveforms for t en sdo 3k 20pf test point v cc t dis waveform 2, t en t dis waveform 1 1860 tc01 sck sdo v il t ddo t hdo v oh v ol 1860 tc02 1860 tc03 conv sdo t en sdo t r t f 1860 tc04 v oh v ol test circuits voltage waveforms for t dis sdo waveform 1 (see note 1) v ih t dis 90% 10% sdo waveform 2 (see note 2) conv note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control 1860 tc05 LTC1860 operation operating sequence the LTC1860 conversion cycle begins with the rising edge of conv. after a period equal to t conv , the conversion is finished. if conv is left high after this time, the LTC1860 goes into sleep mode drawing only leakage current. on the falling edge of conv, the LTC1860 goes into sample mode and sdo is enabled. sck synchronizes the data transfer with each bit being transmitted from sdo on the falling sck edge. the receiving system should capture the data from sdo on the rising edge of sck. after completing the data transfer, if further sck clocks are applied with conv low, sdo will output zeros indefinitely. see figure 1. analog inputs the LTC1860 has a unipolar differential analog input. the converter will measure the voltage between the in + and in C inputs. a zero code will occur when in + minus in C equals zero. full scale occurs when in + minus in C equals v ref minus 1lsb. see figure 2. both the in + and in C inputs are sampled at the same time, so common mode noise on the inputs is rejected by the adc. if in C is grounded and v ref is tied to v cc , a rail-to-rail input span will result on in + as shown in figure 3. reference input the voltage on the reference input of the LTC1860 (and the ltc1861 msop package) defines the full-scale range of the a/d converter. these adcs can operate with reference voltages from v cc to 1v. applicatio s i for atio wu uu
9 LTC1860/ltc1861 18601f figure 1. LTC1860 operating sequence figure 3. LTC1860 with rail-to-rail input span figure 2. LTC1860 transfer curve applicatio s i for atio wu uu conv t conv sck sdo 12 11 10 9 8 7 6 5 4 3 2 1 b11 b10b8b6b4b2b0* hi-z 1860 f01 hi-z b9 b7 b5 b3 b1 sleep mode t smpl *after completing the data transfer, if further sck clocks are applied with conv low, the adc will output zeros indefinitely 0v 1lsb v ref ?2lsb v ref ?1lsb v ref v in * *v in = in + ?in 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1860 f02 1 2 3 4 8 7 6 5 v ref in + in gnd v cc sck sdo conv LTC1860 1860 f03 v in = 0v to v cc v cc 1 m f serial data link to asic, pld, mpu, dsp or shift registers ltc1861 operation operating sequence the ltc1861 conversion cycle begins with the rising edge of conv. after a period equal to t conv , the conversion is finished. if conv is left high after this time, the ltc1861 goes into sleep mode. the ltc1861s 2-bit data word is clocked into the sdi input on the rising edge of sck after conv goes low. additional inputs on the sdi pin are then ignored until the next conv cycle. the shift clock (sck) synchronizes the data transfer with each bit being trans- mitted on the falling sck edge and captured on the rising sck edge in both transmitting and receiving systems. the data is transmitted and received simultaneously (full du- plex). after completing the data transfer, if further sck clocks are applied with conv low, sdo will output zeros indefinitely. see figure 4. analog inputs the two bits of the input word (sdi) assign the mux configuration for the next requested conversion. for a given channel selection, the converter will measure the voltage between the two channels indicated by the + and C signs in the selected row of the following table. in single-ended mode, all input channels are measured with respect to gnd (or agnd). a zero code will occur when the + input minus the C input equals zero. full scale occurs when the + input minus the C input equals v ref minus 1lsb. see figure 5. both the + and C inputs are sampled at the same time so common mode noise is rejected. the input span in the so-8 package is fixed at v ref = v cc . if the C input in differential mode is grounded, a rail-to-rail input span will result on the + input. reference input the reference input of the ltc1861 so-8 package is internally tied to v cc . the span of the a/d converter is therefore equal to v cc . the voltage on the reference input of the ltc1861 msop package defines the span of the a/ d converter. the ltc1861 msop package can operate with reference voltages from 1v to v cc .
10 LTC1860/ltc1861 18601f figure 4. ltc1861 operating sequence mux address table 1. multiplexer channel selection sgl/diff 1 1 0 0 odd/sign 0 1 0 1 channel # 0 + + 1 + + gnd 186465 tbl1 single-ended mux mode differential mux mode conv sdi sck 12 11 10 9 8 7 6 5 4 3 2 1 sdo b11 b10b8b6b4b2b0* hi-z b9 b7 b5 b3 b1 s/d o/s don? care don? care t conv 1860 f04 sleep mode *after completing the data transfer, if further sck clocks are applied with conv low, the adc will output zeros indefinitely hi-z t smpl figure 5. ltc1861 transfer curve 0v 1lsb v cc ?2lsb v cc ?1lsb v cc v in * *v in = (selected ??channel) (selected ?channel) refer to table 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1860 f05 applicatio s i for atio wu uu general analog considerations grounding the LTC1860/ltc1861 should be used with an analog ground plane and single point grounding techniques. do not use wire wrapping techniques to breadboard and evaluate the device. to achieve the optimum performance, use a printed circuit board. the ground pins (agnd and dgnd for the ltc1861 msop package and gnd for the LTC1860 and ltc1861 so-8 package) should be tied directly to the analog ground plane with minimum lead length. bypassing for good performance, the v cc and v ref pins must be free of noise and ripple. any changes in the v cc /v ref voltage with respect to ground during the conversion cycle can induce errors or noise in the output code. bypass the v cc and v ref pins directly to the analog ground plane with a minimum of 1 m f tantalum. keep the bypass capacitor leads as short as possible. analog inputs because of the capacitive redistribution a/d conversion techniques used, the analog inputs of the LTC1860/ ltc1861 have capacitive switching input current spikes. these current spikes settle quickly and do not cause a problem if source resistances are less than 200 w or high speed op amps are used (e.g., the lt ? 1211, lt1469, lt1807, lt1810, lt1630, lt1226 or lt1215). but if large source resistances are used, or if slow settling op amps drive the inputs, take care to ensure the transients caused by the current spikes settle completely before the conver- sion begins.
11 LTC1860/ltc1861 18601f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) u package descriptio ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660) msop (ms8) 1001 0.53 0.015 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.077) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) 0.13 0.05 (.005 .002) 0.86 (.034) ref 0.65 (.0256) bcs 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.88 0.1 (.192 .004) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 0.52 (.206) ref 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.04 (.0165 .0015) typ 0.65 (.0256) bsc msop (ms) 1001 0.53 0.01 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) 0.13 0.05 (.005 .002) 0.86 (.034) ref 0.50 (.0197) typ 12 3 45 4.88 0.10 (.192 .004) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) note 4 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.2 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
12 LTC1860/ltc1861 18601f lt/tp 0502 2k ? printed in usa related parts ? linear technology corporation 2001 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com part number sample rate power dissipation description 12-bit serial i/o adcs ltc1286/ltc1298 12.5ksps/11.1ksps 1.3mw/1.7mw 1-channel with ref. input (ltc1286), 2-channel (ltc1298), 5v ltc1400 400ksps 75mw 1-channel, bipolar or unipolar operation, internal reference, 5v ltc1401 200ksps 15mw so-8 with internal reference, 3v ltc1402 2.2msps 90mw serial i/o, bipolar or unipolar, internal reference ltc1404 600ksps 25mw so-8 with internal reference, bipolar or unipolar, 5v 14-bit serial i/o adcs ltc1417 400ksps 20mw 16-pin ssop, unipolar or bipolar, reference, 5v ltc1418 200ksps 15mw serial/parallel i/o, internal reference, 5v 16-bit serial i/o adcs ltc1609 200ksps 65mw configurable bipolar or unipolar input ranges, 5v ltc1864/ltc1865 250ksps 4.25mw so-8, ms8, 1-channel, 5v/so-8, ms10, 2-channel, 5v references lt1460 micropower precision series reference bandgap, 130 m a supply current, 10ppm/ c, available in sot-23 lt1790 micropower low dropout reference 60 m a supply current, 10ppm/ c, sot-23 u typical applicatio + + 0.1 f 0.1 f 0.1 f 0.1 f 1 f 1 f 0.1 f1 f 100 100 28.7k 10k 4.096v ref 5v 5v 5k 5k 10k 20k 100pf 100pf 5pf 1/2 lt1492 1/2 lt1492 f 1 (0v to 0.66v) f 2 (0v to 2v) 8 4 2 81 7 6 5 4 3 4.096v ref LTC1860 in + in v cc gnd conv sdo sck ref 1860 ta03 sample two channels simultaneously with a single input adc

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